Embodiments of the present invention relate to an improved method and circuit for measuring a minimum (Vmin) and maximum (Vmax) operating voltage of a static random access memory (SRAM) cell of a semiconductor integrated circuit.
Shrinking semiconductor integrated circuit feature sizes have placed increasing challenges on semiconductor integrated circuit testing. In particular, semiconductor integrated memory circuits require complex production testers to determine memory pattern sensitivity at various voltages and temperatures. In addition, parametric test systems are frequently employed in a production environment to determine various operating parameters of individual memory cells. Present sub-micron feature sizes and reduced operating voltages require precise determination of memory cell operating parameters such as trip voltage (Vtrip), minimum and maximum operating voltages, static noise margin, data retention, and others. Second order effects that might have been ignored a decade ago are now critical to reliable and cost-effective circuit operation as will be explained in detail.
FIG. 1 is a block diagram of a parametric test system 100 of the prior art. The parametric test system includes several programmable source measure units (SMUs) 102 and a suitable receptacle or socket 104 for a device under test (DUT). Each source measure unit is arranged to either force voltage and measure current or force current and measure voltage. The DUT may be a production memory circuit operating in a design for test mode or a test circuit for measuring a specific parameter.
Turning now to FIG. 2A, there is a six transistor (6-T) static random access memory (SRAM) cell of the prior art. The 6-T cell includes P-channel drive transistors 202 and 204 and N-channel drive transistors 210 and 212. The drive transistors are connected in a cross coupled manner between true storage node (SNT) 230 and complementary storage node (SNB) 232 as shown to form a latch. N-channel access transistors 206 and 208 couple the latch to true bit line (BLT) data terminal 214 and complementary bit line (BLB) data terminal 216, respectively, in response to a high level of word line (WL) 200 for read and write operations. Alternatively, a low level of word line 200 turns off access transistors 206 and 208 to isolate the memory cell from BLT 214 and BLB 216 and store a data state. As shown, the data state of the memory cell is a true one when the SNT node stores a ‘1’ and the SNB node stores a ‘0’. In this state, transistors 202 and 212 are on and transistors 204 and 210 are off. By convention, the true bit line current (IBLT) and the complementary bit line current (IBLB) are defined as positive current from the respective bit line into the memory cell.
Referring now to FIG. 2B, there is a timing diagram of a memory cell minimum disturb operating voltage (Vmindis) test of the prior art. Vmindis is the minimum voltage at which the memory cell does not fail during read disturb. Supply voltage VSS is held at a low or reference level throughout the test. Bit line voltages VBLT and VBLB are held at a high level throughout the test. A true one (FIG. 2A) is initially written into the memory cell. Supply voltage VDD and word line voltage VWL are incrementally stepped to successively lower voltages 220-224 and 230-234, respectively, as IBLB is monitored. IBLB is initially high due to current flow through N-channel transistors 208 and 212. At a sufficiently low voltage, however, the memory cell changes state so that transistors 204 and 210 are on and transistors 202 and 212 are off. When transistor 212 is off, current flow through series-connected transistors 208 and 212 abruptly drops to zero as shown at 240. This abrupt drop in current IBLB identifies Vmin as the voltage between step 222 and step 224. Accuracy of this measurement depends on resolution of the VDD steps as well as the test equipment. The present inventors have identified a need for improvement as will be discussed in detail.